The present invention relates generally to memory devices and the like, and in particular to a method of correcting over-erased dual bit memory devices.
Many different types and styles of memory exist to store data for computers and similar type systems. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory are all presently available to accommodate data storage.
Each type of memory has its own particular advantages and disadvantages. For example, DRAM and SRAM allow individual bits of data to be erased one at a time, but such memory loses its data when power is removed. EEPROM can alternatively be easily erased without extra exterior equipment, but has reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lacks erasability.
Flash memory, has become a popular type of memory because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power, and thus is nonvolatile. It is used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
Flash memory is generally constructed of many memory cells where single bits of data are stored in and read from respective memory cells. The cells in such structures are programmed and erased by adjusting threshold voltages of these cells by, for example, programming by hot electron injection and erasing by Fowler-Nordheim tunneling. As with many aspects of the semiconductor industry, there is a continuing desire to scale down device dimensions to achieve higher device packing densities on semiconductor wafers. Similarly, increased device speed and performance are also desired to allow more data to be stored on smaller memory devices. Accordingly, there are ongoing efforts to, among other things, increase the number of memory cells that can be packed on a semiconductor wafer.
Individual memory cells are organized into individually addressable units or groups, which are accessed for read, program, or erase operations through address decoding circuitry. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data For instance, many conventional memory cells include a stacked gate metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry, as well as circuitry to provide voltages to the cells being operated on.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the memory cell. In an erase or write operation the voltages are applied so as to cause a charge to be removed or stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed.
The single bit memory cell generally has a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
In a NOR configuration, the control gate is connected to a wordline associated with a row of memory cells to form sectors of such cells. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. Respective drain terminals of the transistors within a single column are connected to the same bitline. In addition, respective flash cells associated with a given bitline have stacked gate terminals coupled to a different wordline, while all the flash cells in the array generally have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using the peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Another memory technology is dual bit memory, which allows multiple bits to be stored in a single cell. In this technology, a memory cell is essentially split into two substantially identical (mirrored) parts, each of which is formulated for storing one of two independent bits. Each dual bit memory cell, like a traditional cell, has a gate with a source and a drain. However, unlike a traditional stacked gate cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, respective dual bit memory cells can have the connections of the source and drain reversed during operation to permit the storing of two bits.
In a virtual ground type architecture, some forms of dual bit memory cells have a semiconductor substrate with implanted or epitaxy-grown conductive bitlines. A multilayer storage layer, referred to as a xe2x80x9ccharge-trapping dielectric layerxe2x80x9d, is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a first insulating layer, a charge-trapping layer, and a second insulating layer. Wordlines are formed over the charge-trapping dielectric layer substantially perpendicular to the bitlines.
Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that a first bit is stored by the source and drain being connected in one arrangement and a second bit is stored by the source and drain being interchanged in another arrangement. Erasing is performed as a blanket operation wherein an array or sector of cells can be simultaneously erased. Generally, a gate voltage is applied to the control gates via the wordline(s) and a drain-voltage is applied to the drains via the bitlines. The sources are configured to float or ground.
A suitable mechanism for programming dual bit memory cells is hot electron injection, which involves applying appropriate voltage potentials to each of the gate electrode, the source, and the drain of the memory device for a specified duration until a charge storing layer accumulates charge. A suitable mechanism for erasing dual bit memory cells is hot hole injection, which involves applying appropriate voltage potentials to the gate electrode and the drain, while floating or grounding the source, to erase a bit of one of the memory cells. These potentials are applied for a specific duration (i.e., pulsed). Conversely, the other bit of the cell is erased by floating the drain and applying appropriate voltage potentials to the source and the gate. Alternatively, both the normal and complementary bits can be erased simultaneously
As stated above, erasing of flash memory is a blanket operation in which cells within an array are typically erased simultaneously. Erasing of the memory cells can be accomplished by repeated applications of short erase pulses, as described above. After each erase pulse, an erase verification can be performed to determine if each cell in the array is xe2x80x9cunder-erased,xe2x80x9d (i.e., whether the cell has a threshold voltage above a predetermined limit). If an under-erased cell is detected, an additional erase pulse can be applied to the entire array. With such an erase procedure, cells that are not under-erased will also be repeatedly erased, leading to some cells becoming xe2x80x9cover-erasedxe2x80x9d before other cells are sufficiently erased. A memory cell having a threshold voltage erased below a predetermined limit is commonly referred to as being over-erased. In this case, the charge storing layer of the over-erased cells is depleted of electrons and becomes positively charged.
An over-erased condition is undesirable for many reasons. For instance, the programming characteristics of an over-erased cell deteriorate more rapidly, affecting, among other things, the number of times that a cell can be reprogrammed. Over-erased cells are also undesirable because they can cause bitline leakage current during program and/or read procedures.
In view of the foregoing, a need exists for a device and method of erasing an array of multi-bit memory cells, which mitigates over-erase and problems associated therewith.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, its primary purpose is merely to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention mitigates over-erase conditions in flash memory devices and also mitigates undesireable effects caused by over-erased flash memory cells by correcting over-erased flash memory cells after an erase procedure. The present invention includes a corrective action that employs a negative gate stress to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. Application of the negative gate stress causes threshold voltages for over-erased cells (i.e., cells that have a threshold voltage below a certain value) to increase, but does not substantially alter threshold voltages for normal or properly erased memory cells.
A method of the present invention operates on an array of dual bit flash memory cells. A block erase operation is performed that erases memory cells of the array. The erase operation is verified and repeated if necessary. Application of negative gate stress is performed as a block operation by applying a negative gate voltage to gates of the memory cells and connecting active regions and a substrate of the memory cells to ground. The negative gate stress is applied with a negative gate voltage and a duration that should correct over-erased cells of the array, if present, without substantially altering non-over-erased or properly erased cells of the array.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which one or more aspects of the present invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the annexed drawings.